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Реферат Physical Methods of Speed-Independent Module Design

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Текст реферата Physical Methods of Speed-Independent Module Design

Physical Methods of Speed-Independent Module Design
Oleg Izosimov
INTEC Ltd, Room 321, 7a Myagi Street, Samara 443093, Russia
1. Introduction
Any method of logic circuit design is based on using formal models of
gates and wires. The simplest model of a gate is determined by only
two "parameters": (a) Boolean function is to be calculated, (b) fixed
propagation delay. The simplest model of a wire is an ideal medium
with zero resistance and consequently, with zero delay. Such simple
models allow circuit design procedures which are a sequence of
elementary steps easily realized by a computer.
When logic circuits designed by using the simplest models expose
unreliable operation as in the case of gate delay variations,
designers introduce less convenient but more realistic models with
arbitrary but finite delay. Using more complicated models may produce
logic circuits that are called speedindependent [1].
In speedindependent circuits transition duration can be arbitrary.
So a centralized clock cannot be used. Instead special circuitry to
detect output validity is applied. Besides, additional interface
circuitry is needed to communicate with the environment in a
handshaking manner. A speedindependent circuit can be seen as a module
consisting of combinational logic (CL) proper, CL output validity
detector (OVD) and interface circuitry (Fig.1). To enable OVD to
distinguish valid output data from invalid ones, the redundant coding
scheme was proposed [2]. The main idea of the scheme is to enumerate
all possible input and output data, both valid and invalid. The OVD
must be provided with appropriate information on data validity. To
realize the idea of redundant coding some constraints on CL design are
imposed [3]
(i) CL must be free of delay hazards, i.e. CL output data word must
not be dependent on the relative delay of signal paths through CL.
(ii) In changing between input states, any intermediate or transient
states that are passed through must not be mapped by CL onto valid
output states.
When these constraints were formulated, the circuit designers
realised that not every Boolean description could be implemented in a
speedindependent style. Other approaches to speedindependent module
design were needed.
SIM design as a science has two branches: logical and physical. For
a long time physical branch was overshadowed in spite of its
competitiveness. The main properties of physical approach to SIM
design are:
(a) Arbitrary coding scheme.
(b) Conventional procedure of operational unit design.
(c) Races of signals in SIM do not affect on its proper operation.
In this paper we propose an approach based on the physical nature of
transitions in CL. We believe that each transition is actually a
transfer of energy which can be naturally detected by physical
From the viewpoint of a radio engineer CL behaves like a radio
transmitter. It emits radio frequencies in the 10 8 -10 10 Hz band
modulated by signals of 10 6 -10 8 Hz.